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MK31VT864-10YE (98.09.03)
Semiconductor
MK31VT864-10YE
8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK):
DESCRIPTION
The Oki MK31VT864-10YE is a fully decoded, 8,388,608 x 64bit synchronous dynamic random access memory composed of eight 64Mb DRAMs (8Mx8) in TSOP packages mounted with decoupling capacitors on a 144-pin glass epoxy Small-outline Dual-in-Line Package supports any application where high density and large capacity of storage memory are required, like for example Mobile PC or PDAs.
FEATURES
* * * * * * * 8-Meg Word x 64-bit (1Bank 8Byte) organization 144-pin Small-Outline Dual Inline Memory Module Single 3.3V power supply, 0.3V tolerance Input :LVTTL compatible Output :LVTTL compatible Refresh : 4,096 cycles / 64 ms Programmable data transfer mode * /CAS latency (2, 3) * Burst length (2, 4, 8) * Data scramble (sequential, interleave) /CAS before /RAS auto-refresh, Self-refresh capability Serial Presence Detect (SPD) With EEPROM
* *
PRODUCT ORGANIZATION
Product Name Operation Frequency (Max.) 100 MHz Access Time (Max.) tAC2 tAC3 9.0ns 9.0ns
MK31VT864-10YE
Note. Specification are subject to change without notice.
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MK31VT864-10YE (98.09.03)
BLOCK DIAGRAM
CKE0 /CS0 DQMB0 DQ0 DQ7 DQMB1 DQ8 DQ15 DQMB2 DQ16 DQ23 DQMB3 DQ24 DQ31 DQMB /CS CKE DQ0 DQMB4 DQ32 DQ39 DQMB5 DQ40 DQ47 DQMB6 DQ48 DQ55 DQMB7 DQ56 DQ63 DQMB /CS CKE DQ0
1
DQ7 DQMB /CS CKE DQ0 DQ7
5
2
DQMB /CS CKE DQ0
6
DQ7 DQMB /CS CKE DQ0
DQ7 DQMB /CS CKE DQ0
3
DQ7 DQMB /CS CKE DQ0 DQ7
7
DQMB /CS CKE DQ0
4
DQ7 DQ7
8
SCL
9
A0 A1 A2
SDA
1
CLK0
2
CLK1
3 7
4 8
5
6
/RAS,/CAS,/WE A0-A11,BA0,BA1
1
a
Vcc
8
SDRAMs Vss 0.22uF x8
Note. The Value of all resistors is 10.
MODULE
OUTLINE
(Front) (Back)
1 2
59 61 60 62
143 144
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MK31VT864-10YE (98.09.03)
PIN CONFIGURATION
Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Front Pin name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss N.C N.C CLK0 Vcc /RAS /WE /CS0 /CS1 Back side Pin No. Pin name 2 Vss 4 DQ32 6 DQ33 8 DQ34 10 DQ35 12 Vcc 14 DQ36 16 DQ37 18 DQ38 20 DQ39 22 Vss 24 DQMB4 26 DQMB5 28 Vcc 30 A3 32 A4 34 A5 36 Vss 38 DQ40 40 DQ41 42 DQ42 44 DQ43 46 Vcc 48 DQ44 50 DQ45 52 DQ46 54 DQ47 56 Vss 58 N.C 60 N.C 62 CKE0 64 Vcc 66 /CAS 68 CKE1 70 N.C 72 N.C Front side Pin No. Pin name 73 N.C 75 Vss 77 N.C 79 N.C 81 Vcc 83 DQ16 85 DQ17 87 DQ18 89 DQ19 91 Vss 93 DQ20 95 DQ21 97 DQ22 99 DQ23 101 Vcc 103 A6 105 A8 107 Vss 109 A9 111 A10 113 Vcc 115 DQMB2 117 DQMB3 119 Vss 121 DQ24 123 DQ25 125 DQ26 127 DQ27 129 Vcc 131 DQ28 133 DQ29 135 DQ30 137 DQ31 139 Vss 141 SDA 143 Vcc Back side Pin No. Pin name 74 CLK1 76 Vss 78 N.C 80 N.C 82 Vcc 84 DQ48 86 DQ49 88 DQ50 90 DQ51 92 Vss 94 DQ52 96 DQ53 98 DQ54 100 DQ55 102 Vcc 104 A7 106 BA0 108 Vss 110 BA1 112 A11 114 Vcc 116 DQMB6 118 DQMB7 120 Vss 122 DQ56 124 DQ57 126 DQ58 128 DQ59 130 Vcc 132 DQ60 134 DQ61 136 DQ62 138 DQ63 140 Vss 142 SCL 144 Vcc
Pin Name Vcc Vss CLK# /CS# CKE# A0-A11 BA0, BA1
Function Power Supply (3.3V) Ground (0V) System Clock Chip Select Clock Enable Address Bank Select Address
Pin Name /RAS /CAS /WE DQMB# DQ# SDA SCL N.C
Function Row Address Strobe Column Address Strobe Write Enable Data Input / Output Mask Data Input / Output Data I/O for SPD CLK input for SPD No Connection
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MK31VT864-10YE (98.09.03)
SERIAL PRESENCE DETECT
Byte No.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90
SPD Hex Value 80 08 04 0C 09 01 40 00 01 A0 90 00 80 08 00 01 0E 04 06 01 01 00 06 F0 90 00 00 1E 14 1E 3C 10 30 10 30 10 00-00 02 5A 41,45,20,20,20,20,20,20 01 / 06
Remark Defines the number of bytes written into SPD memory Total number of bytes of SPD memory Fundamental memory type Number of rows Number of columns Number of module banks Data width of this assembly ... Data width continuation Voltage interface level Cycle time (CL=3) Access time from CLK (CL=3) DIMM configuration type Refresh rate / type Primary SDRAM width Error checking SDRAM width Minimum CLK delay Burst lengths supported Number of banks on each SDRAM /CAS latency /CS latency /WE latency SDRAM module attributes SDRAM device attributes : General Cycle time (CL=2) Access time from CLK (CL=2) Cycle time (CL=1) Access time from CLK (CL=1) Minimum ROW pulse width /RAS to /RAS bank delay /RAS to /CAS delay Minimum /RAS precharge time Density of each bank on module
Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time
Notes 128 byte 256 byte SDRAM 12 rows 9 columns 1 bank 64 bits 0 bits LVTTL CL=3 tCC=10ns CL=3 tAC3=9ns Non Parity Normal / Self x8 tCCD: 1 CLK 2, 4, 8 4 banks 2,3 0 0
Data Signal Input Setup Time Data Signal Input Hold Time SPD data revision code Checksum for byte 0-62 Manufacturer's JEDEC ID code Manufacturing location Manufacturer's part number Revision code R.F.U Intel specification frequency Intel specification /CAS latency Unused storage locations
CL=2 tCC2=15ns CL=2 tAC2=9ns Not support Not support tRP=30ns tRRD=20ns tRCD=30ns tRAS=60ns 64MB 3ns 1ns 3ns 1ns R.F.U 0.2
4D,4B,33,31,56,54,38,36,34, 2D,31,30,59,45,20,20,20,20 20, 20 91, 92 XX-XX 93-125 66 126 06 127 FF-FF 128-255
MK31VT864-10YE
66MHz CL=2, 3
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MK31VT864-10YE (98.09.03)
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating Voltage on any pin relative to Vss Vcc supply voltage Storage temperature Power dissipation Short circuit current Operating temperature Symbol VIN, VOUT Vcc, VccQ Tstg PD* IOS Topr Value -0.5 to Vcc + 0.5 -0.5 to 4.6 - 55 to 125 8 50 0 to 70 Unit V V C W mA C
*: Ta=25C
Recommended Operating Conditions
Parameter Power supply voltage Input high voltage Input low voltage Symbol Vcc, VccQ VIH VIL Min. 3.0 2.0 -0.3 (Voltages referenced to Vss = 0V) Typ. Max. Unit 3.3 3.6 Vcc + 0.3 0.8 V V V
Capacitance
(Vcc = 3.3V 0.3 V , Ta = 25C Parameter Symbol Max. Input capacitance(A0-A11, BA0, BA1) CIN1 40 Input capacitance(/CS0, /RAS, /CAS, /WE, CKE0, DQMB0-7 CIN2 40 I/O capacitance(DQ0 - DQ63 ) CI/O 56 f = 1MHz) Unit pF pF pF
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MK31VT864-10YE (98.09.03)
DC CHARACTERISTICS
(Vcc = 3.3V 0.3V, Ta = 0 to 70C)
Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Stand by) Average Power Supply Current (Clock Suspension) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) Symbol CKE Condition Others Module Spec. Min. Max. Unit Note
VOH VOL ILI ILO ICC1 ICC2 ICC3S
CKE VIH CKE VIH CKE VIL CKE VIH, /CS VIH CKE VIH CKE VIH
IOH = -2.0mA IOL = 2.0mA
-
2.4 -80 -10 -
0.4 80 10 920 320 120
V V A A mA
mA mA
tCC=min. tRC=min.
No Burst
1, 2 3 2
tCC=min. tCC=min.
ICC3 ICC4 ICC5
tCC=min. tCC=min. tCC=min. tRC=min. tCC=min.
-
640 1240 1480
mA mA mA
3 1, 2 2
ICC6
CKE 0.2V
-
16
mA
ICC7
CKE VIL
tCC=min.
-
16
mA
Notes: 1. 2. 3.
Measured with the output open. Address and data can be changed once or not be changed during one cycle. Address and data can be changed once or not be changed during two cycle.
MODE SET ADDRESS KEYS
A6 0 0 0 0 1 1 1 1 Note: /CAS Latency A5 A4 CL 0 0 Reserved 0 1 Reserved 1 0 2 1 1 3 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Burst Type A3 BT 0 Sequential 1 Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 BT=0 0 Reserved 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Reserved BT=1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
A7, A8, A9, A10, A11, BA0, BA1 should stay "L" during mode set cycle.
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MK31VT864-10YE (98.09.03)
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock. 2. After the Vcc voltage has reached the specified level, take a pause of 200s or more with the input being NOP. 3. Enter the precharge all bank command. 4. Apply CBR auto-refresh eight or more times. 5. Enter the mode register setting command.
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MK31VT864-10YE (98.09.03)
AC CHARACTERISTIC
Parameter CL=3 CL=2 CL=3 CL=2 tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tRRD tREF tPDE tT ICCD ICKE IDOZ IDOD IDWD IROH IMRD IOWD Symbol tCC tAC (Vcc = 3.3V 0.3V, Ta = 0 ~ 70C) NOTE 1, 2 . Module Spec. Unit Note Min. Max. 10 15 3 3 3 1 3 3 90 30 60 30 15 20 tSI+1CLK 1 1 2 0 0 2 3 2 9 9 8 1,000,000 64 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle 3, 4 3, 4
Clock Cycle Time Access Time from Clock Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock /RAS Cycle Time /RAS Precharge Time /RAS Active Time /RAS to /CAS Delay Time Write Recovery Time /RAS to /RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time /CAS to /CAS Delay Time (Min) Clock Disable Time from CKE
3
Data Output High Impedance Time from UDQM, LDQM
Data Input Mask Time from DQMB Data Input Time from Write Command Data Output High Impedance Time from Precharge Command. Active Command Input Time from MODE Register Set Command Input (Min) Write Command Input Time from Output NOTES: 1) 2) 3) 4) 5)
AC measurements assume tT=1ns. The reference level for timing of input signals is 1.4V. This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF (RLoad is 50ohm). An access time is measured at 1.4V. If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL. 1.4v 50 OUTPUT OUTPUT LOAD 50pF
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MK31VT864-10YE (98.09.03)
FUNCTION TRUTH TABLE (Table1) (1/2)
Current State Idle /CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L H L L L L L L /RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L /CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L /WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X BA X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X Action NOP NOP 2 ILLEGAL 2 ILLEGAL Row Active 4 NOP 5 Auto-Refresh or Self-Refresh Mode Register write NOP NOP Read Write 2 ILLEGAL Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop 3 Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 2 ILLEGAL Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst Stop 3 Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 2 ILLEGAL 3 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL
Row Active
Read
Write
Read with Auto Precharge
Write with Auto Precharge
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MK31VT864-10YE (98.09.03)
FUNCTION TRUTH TABLE (Table1) (2/2)
Current State Precharge /CS H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L /RAS X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L /CAS X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X /WE X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X Action NOP Idle after tRP NOP Idle after tRP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 4 NOP ILLEGAL NOP NOP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL
AE AE
Write Recovery
Row Active
Refresh
AE AE
Auto Resister Access
ABBREVIATIONS
RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge NOP = No Operation command
Notes: 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle.
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MK31VT864-10YE (98.09.03)
FUNCTION TRUTH TABLE (CKE) (Table2)
Current State(n) Self Refresh CKEn-1 H L L L L L L H L L L L L L H H H H H H H H L H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X H L L L L L L X X X X X /RAS X X H H H L X X X H H H X X X X H H H L L L X X X X X /CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X /WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down ABI Exit Power Down ABI ILLEGAL ILLEGAL 6 ILLEGAL NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension
AE AE
Power Down
AE AE
All Banks idle (ABI)
6
Any State Other than Listed Above
Notes:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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